Electronic counter circuit selectively responsive to input pulses for forward or reverse



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Mw 0M TTOPA/EV United States Patent O 3,155,336 ELECIRNIC CUNTER CiRClUiT SELECTIYELY RESPGNSEVE ''lNPUfpifsES FR FRWARD R REVERSE Roy A. Hempel, Phoenix, Aria., assigner, by mesne assignments, to Textron Electronics, Inc., Providence, RL, a corporation of Belau/are' Filed July 27, 1959, Ser. No. 529,871) Z Claims. (Cl. Sill-88.5)

This invention relates to an electronic counter circuit of the type having multiple states of stable equilibrium and more particularly relates to features of novelty incorporated in such'a circuit facilitating improved and more versatile performance thereof.

In electronic counter circuits of the type forming the subject matter of my application, Serial No. 609,131, tiled September 11, 1956, now Patent 3,038,558, active circuit elements such as transistors are intercoupled to have multiple states of stable equilibrium wherein in each state of stable equilibrium, a different combination of conducting and non-conducting active circuit elements is established.` rIlle circuit is placed in successive states of equilibrium by the impression of electrical impulses of a predetermined polarity to a particular point in the circuit and in each state, a combination of potentials is produced to activate a visual or other means for indicating the count or number of pulses, less than a predetermined number, so impressed. Such impulses may be produced by any of a large number of types of transducers responsive to a wide variety of events or occurrences of a physical or other nature. Accordingly, in combination with such a transducer, this circuit is responsive to give an indication of the number of events or occurrences less than a prede rmined number, taking place. Inlcombination with further identical counters, an indication greater than the predetermined number may be obtained.

It is a primary object of my present invention to further improve the invention disclosed in the aforementioned application by facilitating reverse as well as forward counting of electrical hupulses as hereinabove briefly described. In many applications of a counter, it is desirable to obtain a count of the number of events or occurrences of one type; less, a number of another type. As an example, it may be desirable to obtain a net count ofyobjects passing a particular location, which net count is the number passing in one direction less the num er passing in the opposite direction. Or as another example,'in an electromechanical calculator it may occur that it is necessary to subtract a predetermined number from another number. According to this feature of invention, the circuits may be easily and readily conditioned for count in a forward direction or in a reverse direction in furtherance toward this end.

It is another object of my invention to improve the frequency response of a decade counter circuit in accordance with a novel combination of binary and quinary sections with two and tive active circuit elements, respectively, each section having multiple states of stable equilibrium. In accordance with this feature, a single quinary section output pulse is applied to the binary section input in response to every live pulses applied to the quinary section input and the binary section produces a single output pulse for every two received Vfrom the 3,155,836 Patented Nov. 3, 1964 ICC Itis another object of my invention to provide an elecronic counter indicator circuit operable with low, pulsating direct potential supplyA It is another object of my invention to provide an electronic counter circuit adaptable for operationv at potentials considerably lower than heretofore possible with prior art counters.

It is still another object of my invention to provide an improved circuit for producing a staircase output potential having substantially equal successive increments of direct potential in response to a succession of input pulses.

It is another obiect of my invention to facilitate appropriate extinction of lamp indicators in a counter circuit.

FIGURE 1 shows a binary-quinary reversing decade counter according to the invention; v v FIGURES 2, 3 and 4 represent potential wave forms at points in the' circuit of FIGURE l at different instants of time during forward count; v

FIGURES 5, 6 and 7 represent potential Wave forms at points in the circuit of FIGURE 1 at diiferent instants of time during reverse count; FIGURE 8 shows a *quinary-binary reversing decade counter according to a modified form of the invention;

FIGURES 9, l0 and 11 represent potential Wave forms at points in the circuit of FIGURE 8 at different instants of time during forward count;

FIGURES 12, 13 and 14 represent potential wave forms at points in the circuit of FIGURES at diilerent instants of time during reverse count; v i' FIGURE 15 is a simpliied schematic representation of the binary-quinary decade counter circuitshown in FIGURE 1, including the essential features for forward and reverse operation; Y

FIGURE y16 is a simplified schematic representation of the circuit shown in FIGURE 15 conditioned and effective for achieving forward count; i v

FIGURE 17 is a simplified schematic representation of the circuit shown in FIGURE l5 conditioned and effective for achieving reverse count; 'Y v FIGURE 18 is a simplified schematic representation of the quinary-binary decade counter circuit shown in FIG- URE 8 and including the yessential features for forward and reverse operation; v

FIGURE 19 is a simplified schematic representation of the circuit shown in FIGURE 18 and conditioned forV achieving forward count; i

FIGURE 20 is a lsimplified schematic representation of l the'circuit shown in FIGURE 18 conditioned for achieving reverse count; i i Y n i FIGURE 21 is a simplified schematic representation of the binary-quinary decade counter circuit shown ,in FIGURE l Vand including the vessential circuit elements for resetting the counter to initial condition or zero count; d

FIGURE 22 is a .simplitiedrschematic representation of a modied circuit for achieving reset in a binaryquinary decade counter circuit as shown in FIGURE 1'; FIGURE 23 is a simplified schematic representation of the quinary-binary decade counter circuit shown in FIGURE 8 and including the essential circuit elements lower magv for resetting the counter to initial condition or zero count; n

FIGURE 24 is a simplified schematic representation of a modiiied circuit for achieving reset in a quinarybinary decade counter circuit as shown in FIGURE 8,

FIGURE 25 is a simplified schematic representhatlon of components of a binary-quinary decade counter circuit of of a high potential type as shown in FIGURE 1;

FIGURE 26 is a simplified schematic representation of components of a binary-quinary decade counter circuit having a modified neon lamp connection arrangement and power supply adapting the circuit for low potential operation.

Referring now to FIGURE 1 of the drawings, 8 represents generally the binary-quinary decade counter circuit of the invention having a binary section which receives incoming pulses and delivers an output pulse to the quinary section 12 of the circuit for every two pulses received in the binary circuit. The quinary section is effective in delivering a single output pulse for every iive pulses received from binary section 1t) whereby the circuit as a whole delivers an output pulse for every ten pulses received in its input. A visual indicator section 14 is provided for indicating the number of pulses from zero to nine received subsequent to a reset condition of the counter.

Binary section 10 includes a iirst three element, semiconductor device 16 hereinafter referred to as a transistor comprising a base 18 preferably of N-type semiconducting material as is presently well known, an emitter 20 and a collector 22 both of P-type semi-conducting material and a Second, three element transistor 24 having a base 26 preferably of N-type semi-conducting material, an emitter 28 and a collector 30 both also of P-type semi-conducting material. The transistors 16 and 24 are interconnected with passive circuit elements in a manner so as to provide a iiip-op or direct coupled multivibrator circuit wherein base 18 is coupled to collector 30 through a resistor 32 shunted by a capacitor 34 and base 26 is coupled to collector 22 through a resistor 36 shunted by a capacitor 38. A pair of load resistors 40 and 42 and potentiometers 44 and 46 are serially connected between collectors 22 and 30 and arms 48 and 50 of the potentiometers are coupled to quinary circuit 12 for selectively applying pulses to the quinary in accordance with a preselection hereinafter set forth and described in detail.

For receiving'incoming pulses to the counter circuit from an input terminal 52, a pair of diodes S4 and 56 are connected in series aiding polarity in a closed loop and the respective junctions between diodes are connected to respective bases 18 and 26 to input terminal 52 through respective capacitors 5S and 60. A source of direct potential as indicated as B-lis supplied to the emitters 20 and 28 through lines connected thereto from a terminal 61. Diodes 54 and 56, which are eifective in increasing the frequency reponse of the binary section may be replaced by resistors. However, the unilateral elements are more effective in this function. A

A resetting circuit for the binary section is shown generally at 62 in FIGURES 1 and 2l and is set forth and described in detail hereinbelow in conjunction with the resetting feature of the quinary section.

In normal operation, binary section 10 utilizes a certain value of current which by the generally series arrangement of binary and quinary sections is also utilized in the quinary section. The quinary section, however, requires somewhat greater power for its operation and the binary current is supplemented by an alternate path from potential source B+ through resistor 64 connected to this source and to an adjusable potentiometer 66 in series with a resistor 68 for connection to the emitters of the quinary circuit to be described.

The individual elements of binary circuit 16 are so proportioned as to provide a completely balanced cir- CII i cuit. Transistors 16 and 24 are chosen to be of identical type, resistors 32 and 36 are of the same value, and capacitors 34 and 38 of the same value to approach a balanced symmetrical circuit. It is known, however, that it is a physical impossibility to achieve a perfect balance in such a circuit. Accordingly, in the circuit of binary section 10, upon the application of potential to emitters 20 and 28 from source B+, such an imbalance causes a slightly greater current tiow in one of the transistor collectors over the other, whereby the potential across the load resistor of the greater conducting transistor is increased and such increment is applied to the base of the lesser conducting transistor in such polarity as to reduce the current flow of the lesser conducting transistor. As a consequence, the potential across the load resistor of the lesser conducting transistor is decreased and such decrement is applied to the base of the greater conducting transistor to even further increase its conduction. In a known manner, this action is cumulative and recurs many times in a short period of time whereby one transistor is finally rendered conducting heavily and the other transistor is conducting so lightly as to bc considered cut off or not conducting at all, for all practical purposes. In this stable condition, the base of the cut oif transistor is receptive to signals of the proper polarity to initiate conduction therein which will produce a signal in its output circuit of such polarity as to lessen conduction in the heavily conducting transistor when the signal is applied to its base, and the potential change in the output circuit of such heavily conducting transistor is of such polarity to increase conduction in the previously cut of transistor when applied to its base. This latter action, once initiated, also recurs many times in rapid succession until the formerly cut ofi transistor is conducting heavily and the previously heavily conducting transistor is cut off to form another stable state of equilibrium. Accordingly, two stable states of equilibrium exist for the binary circuit. In one state, a iirst transistor is heavily conducting while the second transistor is cut of and in the other state, the second transistor is heavily conducting while the first transistor is cut olf. During heavy conduction, either of the transistors is unresponsive to potentials applied to the base thereof tending to render the same more conductive. Accordingly, during any one state of equilibrium above described, application of the same pulse of proper polarity to initiate conduction in a transistor, to both of the transistor bases simultaneously, is of the same effect as the application of such a pulse to the cut oil' transistor only. As a consequence, the simultaneous application of an input pulse of the proper polarity at input 52 is eifective to shift the state of equilibrium of transistors and subsequent such pulses cause the state of equilibrium to alternate.

As seen in FIGURE 2 of the drawings, a typical input to the counter may be a series of negative rectangular wave pulses as shown at 53 in the iirst line in this figure. Although the reference line is not shown, it should be understood that all points of this wave are negative. The output potentials appearing at different instants of time at the respective binary transistor collectors are shown at 23 and 3i in the second and third lines of this figure as negative rectangular waves of frequency equal to one-half the input pulse frequency and degrees out of phase with each other. As designated in this gure, t0 represents an initial instant of time at which the binary circuit is reset, with transistor i6 conducting and transistor 24 cut off and the respective collectors at maximum and minimum potentials. At time t1, the leading edge of the first input pulse of wave 53 has passed to initiate the above described sequence of cumulative events in the binary section to render transistor 24 conducting and transistor .i6 cut off. Accordingly, the potential of collector 30 of transistor 24 rises from a minimum to a maximum and the potential of collector 22 of transistor 16 drops from 5 a maximum to a minimum value. As the succceeding incoming pulses are applied, the binary collector potentials reverse at the leading edge of each pulse. It is to be noted, however, the potential at either collector has onehalf the number of leading edges as found in the pulses of the incoming signal.

As explained hereinabovc,-with each change of equilibrium of the transistors, the potential at the collectors thereof changes sharply whereby a pulse is produced at such collector. The negative pulses produced at the collectors 22 and Sti are applied through respective gating circuits 75l and 72, through capacitors 74, 76, 78, 80 and S2 to the bases 34, S6, 88, 90 and 92 of the transistors 14, 95, SS, 1d@ and 102, of the quinary section. Gating circuit 7d includes a capacitor 104 connected in series with a diode 166 :and a resistor 108 connected to the junction therebetween for applying a biasing potential in a manner hercinbelow more fully explained, and gating circuit 72 similarly-'includes a capacitor 11d connected in series with a diode 112 and a resistor 11d connected to the junction therebetween, also for Iapplying a biasing potential derived in a manner to beexplained. Each of the diodes 16 and 112 has its anode connected to ground through the same resistor 115. The anode of the diodes herein are represented by the arrow and the cathode is represented by the straight line. Thus, by the application of a potential across the diodeLpositive at the anode and negative at the cathode, current readily flows since the diode presents a low resistance to such current but in response to a reverse application of potential, that is, positive at the cathode and negative at the anode of each diode, only negligible current ows through the diode since it presents a high resistance to such current., This latter biasing condition is herein referred to as a back bias.

The transistors v94 through 162 of the quinary circuit 12 have bases of N-type semi-conducting material and further include respective emitters 116, 118, 129, 122 and 124 of P-type semi-,conducting material and respective collectors 126, 123, V110, 132 and 134 of lltype semiconducting material. 1n addition to the transistors, quinary 12 includes passive circuit elements intercoupling the transistors in a closed loop to provide a circuit having tive states of stable equilibrium in each of which states, one transistor is cut off and the four others are conducting similar to binary circuit lil. In any such state of equilibrium of the quinary circuit, the cut off transistor is responsive to a pulse of negative polarity of sufficient magnitude applied to its base, to initiate conduction therein with the result that the potential at its collector suddenly rises to apply a positive pulse to components coupled thereto. Similarly, Ia positive pulse of suicient magnitude applied to any quinary circuit transistor base is eltective to change it from a condition-of conduction to one of non-conduction to produce a negative pulse at its collector. l

The base of each transistor of the quinary section is coupled to the collector of eaoh other transistor of this section. Base S4 is coupled to collectors 128, 130, 132 and 134 through respective resistors 136, 138, 14d and 142, base 86 is coupled to collectors 130, 132, 134 and 126 through respective resistors 144, 146, 148 and 159, base 88 is coupled to collectors 132, 134, 126 and 128 through respective resistors 152, 154, 156 and 15S, base 90 is coupled to collectors 134, 126, 128 and 1311 through respective resistors 161i, 162, 164 and 166 and basei2 is coupled to collectors 126, 123, 130 and 132 through respective resistors 163, 171B, 172 4and'174. 'In accordance with a feature of the invention, resistors 150, 153, 166, 174 and .142 are shunted by respective series connected diode-capacitor combinations 176 and 178,Y 180 and 182, 184 and 126, 188 and 190', and 192 and 194 with each diode oriented to have its cathode connected to the capacitor of the combination. For convenient reference, these combinations are hereinafter referred to as the forward set in that in a manner hereinbelow -explained, they are functional to achieve forward count of the circuit. The junctions of the capacitor and diode of these diode-capacitor combinations are coupled to a forward7 line 1% through respective resistors 19S, 2M, 292. 204 and 2do. Additionally, Vresistors 16S, 136, 144, 152 and 16o are shunted by respective series connected capacitor-diode combinations 268 and 210, 212 and 214, 216 and 218, 221i and 222, and 224i and 226 with the cathode or" each diode connected tothe capacitor of the combination. For convenient reference, these combinations are hereinafter referred to as the reverse set in that in a manner also explained hereinbelow, they are functional in achieving reverse count of the circuit. The junctions of the capacitor and diode of these capacitor-diode combinations are coupled through respective resistors 228, 231), 232. 23d 4and 23d to a reverse line 238. Lines 196 and 238 are selectively oonnectable to a ground through a switch 24d having an arm 242 connected to ground and manipulable to engage either of these lines. To assure a circuit return and thus to avoid floating of both of the lines 1% and 238 simultaneously, switch arm 242 necessarily contacts either one or the other of these lines and cannot be disengaged from both except for very minute intervals during switching. The collectors 126, 128, 130, 132 and 13d of the quinary circuits are connected to ground through respective resistors 244, 246, 24d,y 25) and 252. In this arrangement a closed circuit is established whrein each transistor circuit bears the same relationship to, affects and is affected by the transistor circuits adjacent thereto as any other transistor circuit is related to, ailects or is affecte-d by adjacent transistor circuits sirnilarly situa-ted. As an example, the circuit of transistor 96 is related to the circuits of transistors 94 and 9E in the samernanner as the circuit ot transistor 1Go is related to the circuits of transistors 98 and 1612, respectively, or as the circuit of transistor 102 is related to the circuits of transistors 1d@ and 94, respectively. It is to be observed that the circuits of transistors 1412l and 94 are adjacent to each other in that electrically the same are connected as any other adjacent transistor circuits. With this quinary section arrangement, by reason of the diode orientation negative pulses are blocked from passage between a collector to the next adjacent base and provision is made for selectively applying lpositive pulses to the base of onel or the other of the next adjacent transistors,

u depending upon the direction of count desired. A continuous application of such pulses to the bases of transistors on one side of the triggered transistors produces a count in one direction and application of such pulses to the bases of transistors on the other side of the triggered transistors produces a count in the other direction.

The direction of count is controllable by switch 249 which selectively grounds line 1% or line 238. Grounding one of the lines applies zero bias to the negative terminals of the diodes of the set connected to that line. Grounding line 1% applies zero bias to the cathodes of diodes 176, 180, 184, 188 and 192 through'the resistors 193, 2h19, 2512, 234 and 266 and grounding line 233 applies Zerobias to the cathodes of diodes 210, 214, 218, 222 and 226 through resistors 228, 230, 232, 234 and 236. In each instance the remaining, ungrounded line floats at some positive potential above ground since the anode of the diode ol' each set is connected to a collector of a transistor in the quinary section and the positive potentials of these collectors `are applied to the remaining line throughthe diode and resistor extending to the line. As an example, when line 196 is grounded. line 23S oats by reason of the positive potential applied from the collectors to the line through diodes of the reverse set and resistors 228 to 236. Accordingly, the diode of one set, of the cut ott transistor, is biased at zero potential'while the diode of the other set thereor` is biased at the highest `positive potential above ground of any of the collectors of the quinary section. Such positive potential is greater than the magnitude of the positive pulse engendered at the collector of the cut oil? transistor when it is rendered conducting whereby the diode having a positive potential applied to its cathode is suiiiciently back-biased to prevent the passage of positive pulses from the corresponding transistor collector. Purely as an illustration of this feature, it is assumed that switch 249 is connected to line 196 to maintain this line at ground potential and that transistor 96 is cut ofi while the others, viz., 94, 98, 1% and 102, are conducting. A simplified representation of the circuit in this condition is shown in FIGURE 16 wherein the diode-capacitor combinations of the reverse set are omitted as representing in etect an open circuit under these circumstances and the diodes of the forward sets are also omitted since the same merely represent a short circuit under these circumstances. The junction between diode 186 and capacitor 162 being connected to ground through resistor 251i, is at zero bias and therefore, no bias opposition is applied to positive pulses from thc collector 128 through diode 18@ and a low impedance path between collector 128 and base 38 of transistor 98 is established. Diode 214, on the other hand is connected to line 238 tirough resistor 239 and the collectors of the other transistors of the quinary section are coupled to line 238 through respective diodes 216, 213. 222, and 226 and resistors 22S, 232, 234- and 236 to apply the highest positive potential of these collectors to the cathode of diode 214. Accordingly, diode 214 is back-biased at this potential, or in other words a potential in excess of this back-bias, must be applied to the anode of the diode before current tiows therethrough. The elements and potentials of this circuit are selected to apply sutiicient potential back-bias to that diode not having its cathode ground in order to prevent passage of the pulse developed at the coliector of the triggered transistor through this diode.

It is to be noted that upon the passage of the pulse to the next adjacent transistor, that adjacent transistor is cut oit and as explained hereinabove with respect to the circuit of transistor 96, the diodes of the newly cut oi transistor are respectively, back biased for pulse blocking and at ground potential, for appropriate conditioning for pulse transfer in the proper direction when that transistor is triggered.

At each alternation in conduction of the transistors of the binary section, a pulse, either positive or negative is produced at the collectors of these transistors, depending on whether the transistor is rendered conducting or is cut off. For proper operation, only negative pulses from the binary section are applied to the bases of the quinary transistors and therefore. positive pulses are excluded. To this end, gates 72 and 7G are utilized selectively for respective forward and reverse operation of the counter.

Gate 72 is conditioned to pass only negative pulses, while gate 70 is conditioned to block passage of all pulses for forward count.

It is noted that lines 196 and 23S are, respectively, directly connected to the cathode of diodes 112 and 166 whereby the potential existing on these lines are applied to the respective diodes as a bias. In the forward position of switch 240 wherein arm 242 is connected to line 196, to ground the same, a zero bias is applied to the cathode of diode 112. Therefore, this diode imposes no appreciable opposition to negative pulses applied thereto through capacitor 110 from collector 3d. Because of its nature and physical orientation, diode 112 blocks passage of positive pulses from collector 30 irrespective of the bias applied to the diode. Under these circumstances, the cathode of diode 12C-6 is biased positively at substantially `the highest potential of the collectors of conducting transistors in the quinary section because line 238 is coupled thereto through diodes in a manner already explained. Consequently, a back bias is applied to the diode 196 imposing opposition to negative pulses applied to the cathode thereof. ln accordance with the proportioning of the circuit elements and potentials utilized, such back bias exceeds the magnitude of negative pulses produced at collector 22. By its nature and orientation in the cir- LJ cuit, diode 106 blocks passage of positive pulses from collector 22. Accordingly, neither negative nor positive pulses are passed through diode 136 from collector 22 when switch 240 is positioned for forward count.

The binary section receives input pulses forming a wave as represented at 53 in the first line of FIGURE 2. Each leading edge of each pulse of wave 53 is eiective to alter the condition of equilibrium in the binary section whereby the potentials at collectors 22 and 30 are as represented by the waves 23 and 31. At time t1, the leading edge of the input pulse causes transistor 16 to be cut off and transistor 24 to be triggered, at time t2, transistor 16 is triggered and transistor 24 is cut off. The potentials existing at collectors of respective transistors 94, 96, 98, 1th) and 102 at different instants of time, are shown by waves 260, 262, 264, 266 and 263 in the fourth, ifth, sixth, seventh and eighth lines of FIGURE 2 wherein it is observed that from time to to t2, transistor 94 is cut oit and rendered conducting at t2 in response to the leading edge of the negative going potential wave of transistor 24. As transistor 94 is rendered conducting at time t2, transistor 96 is cut off until time t., when it becomes conducting and transistor 98 is cut off. At time t6, transistor 98 is rendered conducting and transistor 100 is cut off, at time t8 transistor 10) is rendered conducting and transistor 192 is cut oit and iinally at time tw, a cycle is completed wherein transistor 102 is rendered conducting, transistor 94 is cut off and an output pulse is produced at terminal 270 coupled to collector 126 of transistor 94. At any instant of time, four of the transistors of the quinary section are conducting while only one is cut off.

Upon positioning switch 240 to connect line 238 to ground, the quinary section is conditioned for reverse counting. A simplified representation of the circuit in this condition is shown in FIGURE 17 wherein the forward diode-capacitor combinations are omitted as being in effect an open circuit and diode of the reverse sets are omitted as being in etect short circuits under the circum stances. Assuming for purposes of illustration, that transistor 96 is cut oi, ground potential is applied to the junction between capacitor and resistor of capacitor-resistor combination 212-214 as well as others similarly situated and back bias is applied from now oating line 196 to the junction between diode 180 and capacitor 182 to block the passage of pulses through diode 180. Diode 214 having zero bias, readily passes pulses therethrough to base 34 to cut off transistor 94. Accordingly, the direction of count is reversed from that previously described. When switch 240 is positioned for reverse count, a back bias is applied to diode 112 and back bias is applied to diode 106 from respective lines 196 and 238 whereby diode 112 passes no pulses at all and diode 106 passes only negative pulses at every second input pulse. A rcverse count is achieved wherein the transistors conduct as indicated in FIGURE 5 of the drawings, in response to the succession of incoming pulses shown. Input pulse wave 272 as in the case of forward count, produces potential waves 274 and 276 at collectors 22 and 3) of the binary section which are observed to be of the same form as waves 256 and 258 engendered at these collectors during forward count. The potentials at collectors 126, 128, 131B, 132 and 134 as represented by waves 278, 280, 282, 284 and 286 are observed to be in reverse from waves 260 through 268 in that the cut-olf period proceeds from transistor 102 to transistor 94 in a reverse manner during the reverse count while the cut-off period progresses from transistor 94 to transistor 102 during forward count.

Referring now to FIGURE 2l as well as to FIGURE 1 for an understanding of the resetting feature of the invention, it is observed that reset input terminal 290 is coupled to binary reset circuit 62 and to quinary reset circuit 292 through respective capacitors 294 and 296. Circuit 62 includes a diode 298 having its anode connected to an intermediate point of a potential divider including resistors 330 and 302 serially connected between B+ and 9 a point of lower potential, and its cathode connected to collector 22. Circuit 292, on the other hand, includes a diode 334 having its positive terminal connected to an intermediate point of a voltage divider including resistors 306 and 308 connected between potentiometer 66 and a point of lower potential and its cathode connected to base 34. The resistor elements of the respective potential dividers are so sized and proportioned as to impress on the anode of each diode 298 and 394, a positive, or in other words a forward potential bias, suiciently large in magnitude to equal or slightly exceed the potential appearing at the respective collector 22 and base 84 when these transistors are cut ot and conducting, respectively. Accordingly, positive reset pulses of small magnitude, only slightly larger than pulse required to cause a shift in equilibrium of the binary and quinary circuits are required. It is further to be noted that the orientation of diodes 293 and 304 mutually excludes pulses of any polarity engendered in either section from being transmitted to the other section. Diode 298 is oriented to block positive pulses from collector 22 and diode 334 blocks negative pulses from collector 22. Diode 394 blocks positive pulses from base 34 and diode 293 blocks negative pulses from base S4. Thus, only positive reset pulses applied at terminal 290 reach the respective sections.

Such a pulse applied to collector 22 and base 26 is eiective to render transistor 16 conducting and transistor 24'.

cutoff if not already in this state, or if already in this state it fails to aitect the conduction therein. Such a pulse is applicable to the base 84 of transistor 94 to cut off conduction therein if conducting or to fail to affect the same if not conducting. Such a condition of transistor 94 leaves transistor 94 cut off and transistors 95, 98, 131B and 12 conducting. This is the initial or reset condition of the transistors of the counter circuit.

For providing a visual indication of the number of incoming pulses from 1 to 9 received by the counter circuit, ten neon lamps 312, 314, 316, 31S, 320, 322, 324, 326, 32S, and 330 are provided and have potentials derived from collectors of the binary and quinary transistors applied thereacross to selectively tire or light the same or to allow the lamps to extinguish. One terminal of each of lamps 312, 316, 320, 324 and 328 is connected to a line 332 extending to collector 22 of transistor 16 through a current limiting resistor 3.34 and one terminal of each of lamps 314, 318, 322, 326 and 330 is connected to a line 336 extending to collector of transistor 24 through current limiting resistor 338. The other terminals of lamps 312 and 314 are joined together and connected to output terminal 279 and collector 126 through resistor 340, the other terminals of lamps 316 and 318 are joined and connected to collector 128 through resistor 342, the other terminals of lamps 320 and 322 are joined and connected to collector 130 through resistor 344, the other terminals of lamps 324` and 326 are joined and connected to collector 132 through resistor 346 and the other terminals of lamps 328 and 33d are joined and connected to collector 134 through resistor 348.

t is noted that resistors 334 and 33S are each in tive series circuits including a different neon lamp and a different resistor and that each of these circuits is connected across a different combination of collectors, one of which is in the binary section and the other of which is in the quinary section. Lamp 312 and resistors 334 and 34@ are across collectors 22 and 12e, lamp 314 and resistors 338 and 345) are across collectors 33 and 126, lamp 316 and resistors 334 and 342 are across collectors 22 and 123, lamp 318 and resistors 338 and 342 are yacross collectors 33 and 128, lamp 32.@ and resistors 334 and 344 are across collectors 22 and 130, lamp 322 and resistors 338 and 344 are across collectors 3d and 13d, lamp 324 and resistors 334 and 346 are across collectors 22 and 132, lamp 326 and resistors 338 and 346 are across collectors 3l) and 132, lamp 328 and resistors 334 and 34S are cross collectors 22 and 134 and lamp 33t) and resistors 338 and 343' Y and therefore the lamps remain extinguished.

lamps.

of time across respective circuits of lamps 312, 314, 318, l

32h, 322, 324, 326, 32S and 33d. The circuit elements and potentials of the circuit are so sized and proportioned as to providesuiiicient potential between the collector of a conducting binary section transistor and collector of a non-conducting quinary section transistor to fire or light a lamp while any other combination of potentials at the collectors such as potentials between a conducting binary collector and conducting quinary collector, fails to lire the same.

As observed in FGURE 4, the potential across each lamp circuit varies in a generally square wave manner in response to the input pulses applied to the counter. The potential diiterence between the collector of the conducting transistor of the binary circuit and the collector of the non-conducting transistor of the quinary circuit is greater in each instance, than the potential differences across any other pairs of collectors above described.

his is indicated by a uniquely enlarged portion on each wave and the potential represented by this portion is equal to or greater than that required to re the neon lamp of the corresponding circuit. The potentials represented by other portions of the wave are insufficient to iire the As a specific example, at reset or zero count, at time lo, wherein transistor 16 of the binary is conduct* ing and transistor 94 of the quinary is non-conducting, the potential diterence between the collectors of these transistors is a maximum whereby lamp 312 is iired to indicate zero count. As seen in FlGURE 4, the potentials at all other lamps at time to, are below the maximum After the iirst pulse at time t1, transistor 16 is rendered non-conducting and transistor 24 is rendered conducting. Ac-A cordingly, the potential difference between collectors 3@ and 126 is greatest as indicated on wave 332 at this time, to light lamp 314, indicating count one (l). Lamp 312 extinguishes because the potential thereacross is decreased to a value below its extinguishing potential. With each succeeding input pulse, the lamps are fired by the maximum potential ditlerence across collectors at that instant of time to indicate the number of the count up to 9 after which the next input pulse causes the circuit to reset. Thus, the lamps 312 through 33t) uniquely tire in the sequence 312, 314, 316, 313, 323, v322, 324, 326, 328 and 333 in response to a succession often input pulses and in response to further input pulses, the lamp firing is repeated. Reset prior to the tenth pulse may be obtained by applying a reset pulse at terminal 230 in a manner explained hereinbelow.

According to another feature of my invention, the resistors 340, 342, 344, 346 and 348 and resistors 334 and 333 improve the performance of the circuit by facilitating the unique firing of only that neon lamp corresponding to the count numbers of the circuit. That is, without the provision of these resistors, the lamp indicator circuit is subject to irregular performance Vsuch as simultaneous tiring of more than one of the neon lamps. By the provision of these resistors, however, the current Jdow of the tired lamps is effective to produce a potential drop across appropriate ones of these resistors to reduce to potential applied to others or" the lamps to avoid the possibility of tiring. Thus, purely as an example, in response to an input pulse rendering transistor 16 conducting and transistor 96 non-conducting, appropriately, neon lamp 316 has a firing potential applied across it and it fires since under these circumstances collector 22 is at a maximum positive potential and collector 128 is at a passing from collector 22 of transistor l5 to collector 123 of transistor 96 passes through resistor 334 interposed in line 332 leading to lamp 326 and through resistor 342 leading from the common junction of lamps 316 and 318 to collector 128. Initially, the tiring of lamp 3l6 is favored over other lamps since it is the lamp of the indicator circuit having maximum potential applied across it and in accordance with a characteristic of neon lamps, greater potentials are required to initiate tiring than to maintain the lamp fired or lit. Thus, the potential drop across resistors 334 and 342 lessens the potential applied across other lamps susceptible to firing. In particular, the drop across resistor 342 lessens the potential applied to lamp 3*'8 which has a terminal connected to a terminal of lamp 3l6 and the drop across resistor 334 lessens the potential applied to line 332 and lamps connected thereto, viz., 312, 329, 324 and 328. The decrease in potentials so applied are less than the thing potentials of the neon lamps but greater than the extinguishing potential thereof whereby lamp 314 remains uniquely tired. In accordance with this feature of my invention wider variation in B+ supply potential or wider variation of setting of potentiometer 66 is permitted since higher potentials increase the susceptibility of firing of more than one of the neon lamps through the use of resistors 340 through 348.

An electrical indication of the count received in the counter input may be obtained at ten output pinstl, l, 2, 3, 4, 5, 6, 7, S and 9. Pins 6, 2, 4, 6 and S are connected to collector 3d of transistor 24 through respective resistors 370, 372, 374, 376 and 373 and to collectors E26, 28, i3d, 1,32 and 134 through respective resistors 38d, 332, 384, 385 and 388 and pins ll, 3, 5, 7 and 9 are connected to collector 22 of transistor 18 through resistors 390, 392, 394, 396 and 398 and to collectors 125, 28, 13), l32 and 134- through parallel connected resistor-capacitor cornhinations 49@ and 4t2, 404 and 4%, 4&8 and 41), 4-2 and 414 and ll-6 and 148. Referring to FIGURE 3 of the drawings, for forward count the potential appearing at the pins il through 9 at different instants of time are represented by waves 426, 422, 424, 426, 42S, 436, 432, 434, 436 and 438 wherein for the count of the circuit, the potential at the corresponding pin is a minimum and less than the potential appearing at this pin for any other count. The resistor values of the output line circuitry have been minimized in accordance with good circuit design, to effect a stronger output pulse at the respective output pins. Circuit means responsive to such a rninimum potential may be appropriately actuated for further U external count indication.

For obtaining a staircase potential as shown at 439 at the top of FIGURE 3 of the drawing in which the potential increases in substantially equal step increments in response to successive input pulses applied to the counter, a staircase output line terminal 44'sl is connected to collectors 125, 128, 13?, and 132 through respective variable resistors 442, 444, 446 and 448 adjusted at progressively greater values of resistance in the order named. Resistors 456 and 452 are serially connected across collectors 22 and 3i) and the variable resistor 454 is connected between the junction thereof and line 449. Resistor 45 is of considerably greater resistance than resistors 45@ and 454 and is provided for limiting the potential range of collector 30. As hereinabove explained, the collectors of the binary and quinary circuit transistors are at relatively high potentials during conduction of the transistor and at relatively low potentials during non-conduction thereof. Thus, since the resistors 442, 444, 445, 448, 45t), 452 and 454 interconnect these collectors through staircase line 440, currents iiow from collectors of quinary and binary circuits of relatively high potential to the collector of the quinary circuit of relatively low potential. In so doing, in the different states of equilibrium of the circuit, difierl?. ent potentials are developed at line 440 since the resistors 442, 444, 446 and 44S are of progressively higher value of resistance.

For a further understanding of the operation of the staircase potential producing components, it is noted that at zero count, transistors 24 and 94 are non-conducting with low collector potentials and that all other transistors l5, 95, 98, 10i) and 102 are conducting with high collector potentials. Accordingly, currents tlow from collectors of quinary transistor collectors 123, 136 and 132 through respective resistors 444, 445, and 44S to line 440 and from line 440 collectively through resistor 442 to collector 126. Thus, at the terminal of resistor 442 connected to line 440, a rst staircase potential is produced.

The contribution from collector 22 is negligible because of the high resistance of resistor 452. In response to the nent incoming pulse, transistor 24 is rendered conducting and transistor 16 non-conducting. Under these conditions, thc increased potential of collector 30 is greater than the potential of collector 126 of transistor 94 whereby this potential difference produces a current ilow between these collectors through resistors 45t) and 454 contributing to that current from other quiuary transistor collectors to collector 126. Accordingly, this increased current ilo-w through resistor 442 increases somewhat the potential drop thereacross and therefore, the potential on line 440. Thus, the second step of the staircase is produced. In response to the third incoming pulse, transistors 24 and 9o are nonconducting and the other transisters are conducting. By reason of potential difference at collectors, current flows from collectors 12-5, 130 and 132 through respective resistors 442, 446 and 448 to line 446 and from this line to collector 23 through resistor 444. By the proportioning of resistance values of resistors a potential is produced at line 44) greater than at step two, to produce the third step of the staircase. For the fourth step, the contribution of collector' 30 is added to further increase the staircase potential. In similar manner counts to eight produce eight steps of the wave. ln response to the ninth count, the potential of the quinary transistor collectors 126, 126, 130 and 132 is applied through resistors 442, 444, 445 and 448 directly to line 446 and in response to the tenth pulse an increment from collector 36 of transistor 24 is added through resistors 456 and 454.

For improving the extinguishing action of the neon lamps, diode 458 and capacitor 454 are serially connected between collector 22 and line 332 and diode 462 and capacitor 456 are serially connected between collector 3d and line 335. Resistors 4553 and 46) interconect rcspective the junctions between these serial diode and capacitor combinations and a terminal 463 to which the B-ipotential of terminal 6l is applied. The diodes 453 and 462 are thus biased slightly in the forward direction by this Bi-ipotential and capacitors 464 and 466 are prcvented from building up a large charge. Accordingly, negative pulses from collectors 22 and 30 pass through respective diodes 453 and 462 and respective capacitors 454 and 465 to be applied to terminals of selected neon lamps to appropriately aid their extinction.

The potential values of various parts of the counter circuit shown in FIGURE 1 are shown for reverse count in FlGURES 5, 6 and 7 wherein FIGURE 5 shows respective waves representing the input pulses and potentials at collectors 22 and 3d and the potentials at collectors l26, 128, 35), 132 and 34 as described hereinabove. In FEGURE 6, the waves 484, 486, 43S, 499, 492, 494, 4%, 49S, 5533, 502 and 564 represent, respectively, the potential values at the staircase output terminal 440 and the potentials at pins d through 9 wherein the minimum potential of each latter group of waves represents the cornbination of conducting binary and non-conducting quinary transistors. lt should be observed that the staircase, in this event, is reverse to that in FIGURE 3. In FlGURE 7, the waves 568, Sli), 512, 5M, 516, S18, 529, 522, S24 and All diodes 1N29f5. All transistors 2Nl36 or 2Nl13. Resistors:

68 680 ohms.

411 and 42 1.8K.

244, 246, 248, 25@ and 252 4.7K.

44 and 46 5.0K.

170, 17,2, and 174 22K. 32, 36, 108, 1 14 and 450 33K. 193, 20), 202, 204, 20o, 22S,

393,490, 4114, 403, 412, and

442 25K potentiometer set on approximately 12K.

444 25K potentiometer Set on aproximately 15K.

446 50K potentiometer set on approxig mately 27K.

448 100K potentiometerk setV on approximately 56K.

454 100K potentiometer set for proper staircase Waveform.

300, 302, 3%, 308, 450, and

' 334 and 338 180K.

66 5K potentiometer and 1.5 resistor.

340, 342, 344, 346, and 348 15K.

Capacitors:

74, 7b, 7S, Si), 82, 17S, 132, 186,

and 224 220 mmf.

34 and 38 330 mmf.

5S and 60 68 mmf.

104 and 110 .001 mmf.

294, 296, 464, 466, and 527 .01 mf,

4152, 456, 410, 414, and 41S 180 mmf.

B+ 95 volts.

All neon lamps: 312, 314, 318, 326,

322, 324, 326-, ses, 33e Generar Electric Type Ne-Z neon lamp aged and selected to tire at same voltage.

during conduction to 17.5 volts during cut off and reset pulses are positive at substantially l5 volts. The ten steps of the staircase output voltage are of the order of seven volts total and the individual steps are equal proportions of the total. In a circuit according to the specications as set forth hereinabove, the described binary-quinary decade counter is capable ot' effective, accurate operation within an input frequency of 75 kilocycles per second and without the reversing feature is operable accurately and effectively to a frequency of 35() kilocycles per second. The term frequency as used herein is intended to indicate counts per second.

In accordance with a modilication of the invention as set forth and described in FGURES 8, 9, 10, 11, l2, 13, 14, 18, 19, 20, 23, and 24, the frequency response of a reversing decade counter may be greatly improved by the novel cooperation between binary and quinary circuits wherein a quinary-binary circuit arrangement is established. In this embodiment of the invention, many elements are disposed and function similarly tothe corresponding elements in FIGURE 1 and a similar 95 volt supply potential is applied at pin 6i. Accordingly, these elements are not described with the detail and particularity used in describing similar elements in FIGURE l. Also, for simplicity and clarity, elements having similar structure and `functions are designated by the saine numbers primed.

Incoming pulses are rst received in the quaniary section 12' Vto trigger the transistors thereof and output pulses produced in the quinary section in response to every five input pulses are applied to the binary section 10 wherein a single output pulse is produced from the binary section in response to every two pulses received from the quinary section. Thus, a single output pulse is delivered from the counter as a Whole in response to every ten input pulses applied thereto and the'count of the number of pulses received is indicated by a visual indicator shown generally at14.

The quinary section 12 is similar to quinary section 12 in FIGURE 1 and includes rive transistors 94', 96', 93', lub', and 102', each having a base, emitter. and collector intercoupled with passive circuit elements and a potential source applied to the emitters from the binary section 12 to provide a circuit having ve states of stable equilibrium in each of which states, one of the transistors is cut off and the others are conducting. As described with respect to quinary section 12, the quinary section 12 of FIGURE S includes appropriately biased diodes controlled by a grounding switch 249 for directing the sequence of cut oit and conduction of the quinary section transistors for forward or reverse count.

Input signal pulses to the counter are applied directly to bases of the quinary section transistors at input terminal 631) rather than to the binary section, and each pulsel so applied is eiiective to shift the position of the nonconducting transistor in the quinary in the direction determined by switch 24u.

Y For cooperation with binary section 10' of the counter, the output ot quinary circuit 12' is selectively applied from either collector 126 or 134 of transistors 94' and 192', to the bases 13' and 26' in the binary section through output gate 662 on the one hand or output ygate 694 on the other hand. Gates 602 and 6134 are controllable by proper potential bias to pass pulses or to exclude the same from the binary section. Gate 662 includes a diode 695 having its cathode connected to collector 126 and its anode coupled to bases 18 and 26 of the binary section transistors through a pair of capacitors en?) and 61) connected to anodes `of diodes 54' and 56. During normal operation the collector 126 varies between different values or' positive potential and the positive potential of collector 12o is applied to the cathode of diode 606 tending to apply a back bias thereto. Such a bias would prevent the passage of negative pulses and the orientation of the diode prevents passage of positive pulses engendered at the collector 126'. For facilitating the passage of negative pulses through the diode from collector 126', a potential bias is applicable to the anode of diode 666 through a resistor 612 leading to the reverse terminal of switch 240'. When switch 246' is in forward position, line 238' is -ioating at a potential above ground since it is coupled to the collectors in the quinary section through diodes and resistors extending between this line and the collectors. Such a "floating bias is of a polarity to be a forward bias for diode 666 neutralizing or overcoming the bias applied to the diode from collector 126' and therefore the diode readily passes negative pulses from collector 126 to the binary section bases. In the reverse position of switch 246', line 233' is grounded to apply a zero bias to the anode of diode 666. The potential existing at collector 126' therefore imposes a back. bias on the diode whereby all negative pulses of a magnitude less than the back bias are blocked. Accordingly, under this bias, negative pulses at collector 126' are unaided and are of insufcient magnitude to affect the binary section.

Gate 694 includes a diode 614 having its cathode connected to collector 134' and its anode coupled to bases 26 and 18 through capacitors 616 and 618 and a resistor 620 connected between the anode of diode 614 and forward line 196. In the reverse position of switch 246', line 196 shown in FIGURE 8 is at a positive "floating" potential received from conducting transistor collectors and such potential bias is applied to the anode of diode 614 to permit passage of negative pulses from collector 134' to the binary section transistor bases. In the forward position of switch 246', diode 614 is back biased by the potential of collector 134' to prevent passages of negative pulses.

Typical input pulses are represented at 622 in FIGURE 9 and the potentials at collectors 126', 128', 136', 132' and 134' of the quinary section are represented at 624, 626, 628, 630 and 632 in this ligure. At time t0, transistor 94' is cut off and the potential at collector 126 drops abruptly to a minimum value and at time t1, transistor 94' is triggered, raising its collector otential to e a maximum and transistor $6' is cut oil dropping its collector potential to a minimum. Accordingly, for each ten input pulses, each transistor is cut oli twice and in the succession shown in the waves 624 to 632, in FIG- URE 9. Either transistor 94' or 194' applied two output pulses to the binary for each ten incoming pulses. The transistors of the binary section are shifted in condition of equilibrium in response to each quinary section output pulse occurring at each tive pulses received in the quinary section. passing through gate 662 is as shown at 625 in FIGURE l0. At time te, the pulse delivered from the collector 126 of transistor 94' in the forward direction through gate 602 to the binary section bases, is of sufficient magnitude to cut ofttransistor 16' which triggers transistor 24' whereby the collector potentials of these transistors fall and rise, respectively, to minimum and maximum values. The potentials remain at such values until another negative pulse is applied to the binary bases from collector 126' to shift the position of equilibrium in the binary section and shift the collector potentials to respective maximum and minimum values. The cycle of events is completed when a third negative pulse is produced at collector 126'. The binary collector potentials are shown in FIGURE 9 wherein waves 634 and 636 represent, respectively, the potentials at collectors 22' and 30'. Wave 636, consequently represents also the decade output wave appearing at decade output terminal 637. It is to be observed that wave 633 of FIGURE 10 representing the potential applied to the binary section through gate 664 under these circumstances indicates a small pulse ineffective to trigger the binary section.

For a visual indication of the count from O to 9 received by the counter, ten neon lamps 312' to 330' are connected together with series resistors in circuit across The output wave from collector 126' 1 5 different combinations of quinary and binary transistor collectors. In a manner similar to the binary-quinary decade counter, the neon lamp circuit connected across the collector combination of which the quinary transistor is cut ofi and the binary transistor is conducting, has impressed thereacross a potential in excess of that impressed across other lamp circuits and suflicient to fire the corresponding lamp. As a consequence, the lamp of that circuit fires or lights, but the remaining lamps remain extinguished for lack of sufficient applied potential. In FIGURE 11, the potentials across the different lamp circuits at different times are shown at waves 638, 640, 642, 644, 646, 648, 650, 652, 654 and 656 wherein the respective peaks at times t0, t1, etc., represents potentials sufficiently great to fire corresponding lamps. In response to input pulses received at times to, t1, etc., the lamps tire in order.

It is noted that since the transistors in the quinary section are successively cut oi in response to each incoming pulse rather than each two incoming pulses as in the binary-quinary circuit, the lamp firing potential is derived at such cut off quinary transistor and the fired lamps appear in alternate manner as in FIGURE 8. The neon lamps in FIGURE 8 fire in the sequence 312', 316', 320', 324', 32S', 314', 313', 322', 326', and 330'.

In a manner similar to that shown in FIGURE l, ten pins to 9' are provided for obtaining a potential cxternally applicable for indicating the count of the circuit. The circuitry provided for these pins is the same as shown in FIGURE 1 with the exception that counterparts of the capacitors 402, 406, 410, 414 and 418 are omitted. The potentials derived at pins 0' to 9' are shown at 658, 660, 662, 664, 666, 668, 670, 672, 674, and 676 in FIGURE 10 wherein it is observed that each wave produces a minimum potential at a different instant of time. External circuitry may be connected to these pins to produce an indication of the count. It should be noted that pins 0' to 9 do not appear in orderly sequence but rather in alternate manner since the lamp firing potential is derived in a similar alternate manner.

A staircase output potential is derivable in the circuit of FIGURE 8 in a manner similar to that described with respect to FIGURE 1, wherein terminal 440' is connected to collectors 126', 128', 130' and 132' through variable resistors 442', 444', 446', 448', and 454'. Terminal 440' is also connected to collectors 22' and 30' through respective resistors 466' and 452'. The output derived at terminal 446' is shown graphically at 684 inFIGURE 10.

The resetting circuit 62' of the quinary-binary decade counter shown in FIGURE 8 is a similar in construction and function to the resetting circuit 62 in FIGURE 1 and is effective in resetting the binary section with transistor 16' cut oi and 24 conducting and quinary section resetting circuit 292' is effective in the manner of circuit 222, to reset the quinary section with transistor 94' cut o and the others conducting. In the case of binary section 10', the resetting pulse is applied to the collector 36 of transistor 24' to render the same conducting in response to the positive resetting pulse applied thereto. The resetting pulse applied to the decade counter is effective to render ,transistors 18' and 94' cut oli and all others conducting.

FIGURES 12, 13 and 14 show graphs representing values of potentials at different instants of time and appearing at different points in the circuit of FIGURE 8 when operated for reverse count. In FIGURE l2 the input pulses are indicated at 636, the potentials of quinary section collectors 126', 12S', 130', 132' and 134 at 688, 621), 692, 6&4, and 696, the potentials across neon lamp circuits of FIGURE 14 at 702, 704, 706, 708, 710, 712, '714, 716, 718 and 720, the potentials at output pins 0' to 9 of FIGURE 13 at 722, 724, 726, 728, 736, 732, 734, 736, 733 and 740 and the staircase output potential at 742. Waves 625' and 633' represent, respectively, the potentials passing from collectors 126' and 134' through respective gates 602 and 604. It is observed in each of these figures that the count of the circuit progresses in reverse and that the lamp indicators and external output potentials accordingly are activated in reverse.

In quinary-binary counter circuit constructed as shown in FIGURE 8 and wherein the primed numbered elements are of the same values as corresponding elements in FIGURE l, resistors 612 and 626 are 100K in Value, capacitors 60S, dll), elle, and cl3 are 68 micro microfarads and each ot diodes elle and di: is a lN295, the circuit has been very satisfactorily operated at frequencies in excess of 120 kilocycles per second with forward and reverse gating and at frequencies of approximately 250 kilocycles per second without the reversing features. Accordingly, the quinary-binary counter circuit arrangement of this invention is advantageous over the binary-quinary counter circuit arrangement in that its frequency response with reverse gating is better. As another advantage of the quinary-binary counter circuit arrangement, the steps of the staircase output potential wave are larger in that they are of the yorder of ten volts total for ten steps. It is to be understood that in this embodiment of my invention as Well las others herein described, the specific values of circuit elements are purely examples and that these elements may vary widely in accordance with my invention.

According to another modiication of the invention the binary-quinary decade counter may include circuitry for resetting both binary and quinarj sections as shown in simplified FIGURE 22 of the drawings. Similar elements performing similar functions to corresponding elements in FIGURES l and 2l of the drawings are designated by the same numbers with a double prime. In FIGURE 22, the binary reset circuit 62" comprises a pair of resistors 36d and 302 serially connected between a source of B+ potential and a point of lower potential to form a potential divider for applying a potential bias to the positive terminal of a diode 2.98" connected to the junction point of these resistors and to the kbase 26 of the transistor Zd". A capacitor 294i is interposed between reset input terminal 2% and the junction between 39d" and 302".

For achieving reset of the circuit transistors, reset input terminal 2gb is also coupled to the base 34" of transistor 9'4" through capacitor 2% and diode 3M in series and a potential bias is applied to the anode of diode 394" by connection thereof to the junction of resistors 3616 and 3dS forming a potential divider. In accordance with a feature of this embodiment of my invention, reset terminal 290 is also connected to lamps StZ, 316", 32d, 324 and 328 through a gate 741, including a series arrangement of a diode 744, a capacitor '74,6 and a resistor 334. A potential bias is applied `to the cathode of diode 74d by the connection thereof to the junction between resistors '7dand 759 which in turn are connected between a source of positive potential and ground. ln this circuit, the application of a positive reset pulse at terminal 290 is effective to impress appropriate potentals to the bases 26 and S4" of transistors Zei and 94 and to the terminal of lamp 3l?. remote from its connection to resistor 3ft-tl. The effect of such a pulse is to render transistors 2d and 94 non-conducting and .under the circumstances to raise the potential of lthe terminal of lamp 312 remote from its connection `to resistor 34d sutliciently to produce a potential difference across the neon lamp M2 sufficiently great to cause it to rire. The value of resistor 334i" interposed in the connection between lamp 312 and collector 22 of transistor i6 is suliiciently high to render the eiiect of the reset pulse on transistor le through its collector, negligible, but after reset, the potential of collector 22 applied through this resistor to lamp 3112 is effective to Amaintain a potential diiierence across the lamp to maintain its tiring. The gate circuit 741 thus, facilitates iiring of the reset neon lamp by providing an increased firing potential. In case of martion includes transistors 772 and 774i, the detailed in- 'l ginal lamps, thisfeature minimizes erractic counter performance.

The quinary-binary decade counter may be reset according to another modification of my invention as shown in FIGURE 24 of the drawings wherein elements corresponding to and performing functions similar to eiements in FIGURE 8 are designated by the same number triple primed. Thus, reset circuit 62 is similar to reset circuit e2 with the cathode of diode 298'" connected to base ll'" of transistor lo" rather than to the collector of transistor 24". Reset terminal 290'" is connected to base 34"through capacitor 2976" and diode 304m, the anode of which is biased at a potential appearing at the junction of resistors 306'" and 308'" connected serially between emitter 116'" and collector 126'" of transistor dem. Reset terminal 290' is also connected to one terminal of each of neon lamps 312', diem, 32W", 32.4" and 328'" and through a gate circuit 75l including a diode 752 serially connected with a capacitor 754. The cathode of diode 752 which is connected to capacitor 754 is positively biased by a potential derived at the junction of resistors '758 and 76d serially connected between emitter 116'" and ground. In a manner similar to gating circuit 741 in FIGURE 22, gating circuit 75l facilitates the tiring of neon lamp Slim in response to areset pulse applied to terminal 299'". Collector 36 is connected through resistor 334'" to one terminal of each of neon lamps 312'", 316'",-

SZlm, 324'" and 328'" to maintain firing of these lamps after initially tired and'similarly, lamps SMM, 318'", 322'", 326'", and 330'" are maintained fired, once initiated by the connection of one terminal of each to collector 22" through resistor 334'".

In FIGURE 25 is a simplified schematic diagram of a -binary-quinary decade counter circuit of the type shown in FIGURE l of the drawings which in the typical exam 1le hereinabove set forth may be operated at a B+ potential of volts illustrating the general series circuit arrangement between 'a binary section l@ and a quinary section l2, the details of which are not set forth. FIGURE 26 is a simplified schematic diagram of a binary-quinary decade counter circuit according to still another embodiment of my invention, wherein in accordance with another important feature of my invention, the binary and quinary sections are arranged side by side or in a generally parallel circuit relationship. The structure and function of the individual circuits in each case is substantially the same but as described more fully hereinbelow, the circuit of FIGURE 26 is operable at lower potentials than are required in the circuit of FIGURE 25 with the B+ potential in FIG- URE 26 being less than one third of the B+ potential necessary in FIGURE 25 under circumstances wherein the passive and active circuits are of the same values as corresponding elements in the circuit of FIGUREk l. In the operation of a counter circuit as shown in FIG- URE 25, considerable potential .swing at transistor collectors may be required in achieving tiring and extinction of the neon lamps in the indicator circuit. In accordance with improvements incorporated in the circuit of FlGURE 26, this large potential swing is obviated and operation of the circuit is improved.

In FlGURE 26, the quinary section lincludes transistors 762, 764.", 766, 768 and 770, the .detailed interco'upling Y of which is not shown since it `may be substantially as in the quinary circuits of the :binary-quinary or qumarybinary circuits described hereinabove and `the binary sectercoupling of which is not shown since it also'may be substantially as in the aforedescribed binary circuits.

y In this circuit, a source or" B+ potential is applied to 

1. AN ELECTRONIC COUNTER CIRCUIT COMPRISING A PAIR OF ACTIVE CIRCUIT ELEMENTS EACH HAVING A CONTROL ELECTRODE AND AN OUTPUT ELECTRODE BEING INTERCOUPLED TO FORM A BISTABLE CIRCUIT SECTION HAVING TWO STATES OF STABLE EQUILIBRIUM IN EACH OF WHICH A DIFFERENT ONE OF SAID ACTIVE CIRCUIT ELEMENTS IS CONDUCTING AND THE OTHER IS SUBSTANTIALLY CUT OFF, SAID BI-STABLE CIRCUIT SECTION PRODUCING A PULSE AT SAID OUTPUT ELECTRODE IN RESPONSE TO A CHANGE IN THE STATE OF EQUILIBRIUM THEREOF, INPUT CIRCUIT MEANS COUPLED TO THE CONTROL ELECTRODES OF SAID ELEMENTS FOR APPLYING INPUT PULSES THERETO, FIVE FURTHER ACTIVE CIRCUIT ELEMENTS EACH HAVING A CONTROL ELECTRODE AND AN OUTPUT ELECTRODE, THE CONTROL ELECTRODES AND OUTPUT ELECTRODES OF SAID FURTHER ACTIVE CIRCUIT ELEMENTS BEING INTERCOUPLED TO FORM A MULTI-STABLE CIRCUIT SECTION HAVING FIVE STATES OF STABLE EQUILIBRIUM IN EACH OF WHICH A DIFFERENT ACTIVE CIRCUIT ELEMENT IS SUBSTANTIALLY CUT OFF AND THE OTHERS ARE CONDUCTING, MEANS INTERCONNECTING THE OUTPUT ELECTRODE OF EACH ACTIVE CIRCUIT ELEMENT OF SAID MULTI-STABLE CIRCUIT SECTION TO THE CONTROL ELECTRODE OF EACH OTHER ACTIVE CIRCUIT ELEMENT OF SAID MULTI-STABLE CIRCUIT SECTION, MEANS INCLUDING A PAIR OF DIODES CONNECTING THE OUTPUT ELECTRODE OF EACH ACTIVE CIRCUIT ELEMENT IN SAID MULTI-STABLE CIRCUIT SECTION TO THE CONTROL ELECTRODE OF TWO OTHER ACTIVE CIRCUIT ELEMENTS IN SAID MULTI-STABLE CIRCUIT SECTION, BIASING MEANS FOR SELECTIVELY APPLYING A BIASING POTENTIAL TO ONE OF THE DIODES OF SAID PAIR OF DIODES, MEANS INCLUDING A SECOND PAIR OF DIODES EACH CONNECTING THE OUTPUT ELECTRODE OF ONE OF THE ACTIVE CIRCUIT ELEMENTS OF SAID BI-STABLE CIRCUIT SECTION TO THE CONTROL ELECTRODES OF ALL OF THE ACTIVE CIRCUIT ELEMENTS IN SAID MULTI-STABLE CIRCUIT SECTION, AND BIASING MEANS FOR SELECTIVELY BIASING ONE OF SAID SECOND PAIR OF DIODES TO PREVENT CONDUCTION THERETHROUGH. 